Epitaxial wafer supplier IQE plc said Thursday its newly developed UltraSmooth strained silicon technology has demonstrated speed improvements for both nMOS and pMOS devices below 0.10 microns. IQE ...

Dynamic random-access memory (DRAM) chips contain many other transistors besides the access transistor to enable full operation of the DRAM memory. These peripheral transistors must meet stringent ...

—The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and ...

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up.

The ASIC and Foundry Business Unit at Toshiba Electronics Europe (TEE) has announced that European ASIC and system-on-chip (SoC) customers can now take advantage of eFUSE technology when developing ...

The company offers a glimpse at how it envisions upgrading chip designs after 2025. To create even faster CPUs, Intel is researching stacking “multiple” transistors on top of each to raise the chip ...