EDN

ASIC design flow gives CPU core custom performance

The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce ...
Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
EDN

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
Design-Reuse

Magma and ChipX Extend Integrated RTL-to-GDSII Design Flow to Next-Generation Structured ASIC Designs

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...
Electronic Design

Digital ICs> ASICs

As more logic and memory are integrated onto ASICs, manufacturers and foundries are shifting from 130- to 90-nm design rules. The smaller transistors possible at 90 nm enable a near-fourfold increase ...